In the nanoscale era of Complementary Metal Oxide Semiconductor (CMOS) scaling, the what-you-draw-is-what-you-get approach to layout and circuit design ceases to be predictable, as lithographic, etch, and stress variations affect circuit parameters. Deep sub-wavelength lithography challenges have reduced the lithographic process window and destroyed the ability to reproduce arbitrary layout patterns, thereby making systematic variability a serious impediment to continued scaling. Optical Proximity Correction (OPC) and Resolution Enhancement Techniques (RET) have stepped in to preserve printability, but these techniques have increased mask costs and have constrained the patterns that can be reproduced. Further complicating matters, in today's digital world, many integrated circuit designs require a substantial amount of both memory and logic. Thus, there is a need for an integrated circuit including both memory and logic that can be reliably manufactured using sub-wavelength lithography at reasonable cost.